1. Field of the Invention
This invention relates to the field of data processing devices, and more particularly to a method for facilitating inter-processor communications in a multiprocessing environment.
2. Background Art
Data processing systems adapted for high levels of data throughput and/or for processing large arrays of data typically employ parallel processing to enhance performance. Such systems are commonly built around an array of independent but mutually interconnected processing units. In some systems, a supervisory processor is used to control the operation of all other processors, however, this approach involves significant hardware and processing overhead.
An alternative approach is to eliminate the supervisor and have each processing unit capable of autonomous operation. Supervisory control is thereby accomplished within an operating system common to all of the processors. This approach requires a network of inter-processor communications such that the activities of each processor may be controlled by the operating system and synchronized, when required, with activities of other processors.
Prior art multiprocessor systems have only limited interprocessor communication capabilities. Most prior art systems employ a shared memory through which data may be exchanged by memory operations such as a read-modify-write sequence. Control functions may be effectuated in a similar manner by causing one processor to write to a control word location in shared memory, which location is subsequently read by another processor. Local copies of the shared memory space (or portions thereof) may be maintained by the individual processors. For example, the HEP processor of Denelcor utilizes a form of shared memory communications in which each shared memory location includes a lock bit for controlling access.
Shared memory multiprocessors typically communicate control information via messages sent through shared communication areas in memory. When one processor wishes to send a message to another, it first obtains exclusive access to a predetermined communication area. Exclusive access is obtained either by prior allocation of communication areas or by the use of locks provided by the operating system and implemented via indivisible operation provided by the processor's instruction set (e.g., test-and-set). Once the message has been written to the communication area, the sending processor uses a second mechanism to inform the receiving processor that data has been sent. In some cases, the message simply is left in the communication area, to be read by the receiving processor when it does a periodic poll of its communication areas. In other cases, the sending processor sends a message interrupt to the receiving processor via the bus interconnecting the processors. The receiving processor, upon recognizing the interrupt, processes the incoming message. Message and message interrupt sending typically are operating system functions.
Certain prior art multiprocessor systems have provided an interrupt in the event that a predefined physical address is the target of a memory write operation. However, no information is exchanged between processors in such prior art systems. For example, the IEEE Standard for a Simple 32-bit Backplane Bus, also referred to as NuBus, ANSI/IEEE Std. 1196-1987, provides an interrupt that may be generated by a bus master to interrupt another (slave) module upon performing an event transaction into an area of the address space that is being monitored by the slave module. However, there is no provision for a transfer of information from the bus master to the slave module in conjuction with such an interrupt.